1. Field of the Invention
The present invention relates to a semiconductor memory device and a method of manufacturing the same. In particular, the present invention relates to a semiconductor memory device, in which non-volatile memory cells are highly densely arranged, and highly resistant to a relatively higher voltage, and a method of manufacturing such a semiconductor memory device.
2. Related Art
So-called MONOS (Metal-silicon Oxide-silicon Nitride-silicon Oxide-Semiconductor) memory cell devices, in which electric charge is trapped into silicon nitride layers, are known as one type of non-volatile semiconductor memory devices capable of being electrically written and erased. A MONOS memory cell device is capable of being written and erased at a relatively lower voltage as compared with a floating gate type memory cell device. Further, a MONOS memory cell device, which has a single-gate structure, is more suitable for miniaturization than a floating gate type memory cell device, which requires a multi-layer structure, since the gate aspect ratio of a MONOS memory cell device is smaller than that of a floating gate type memory cell device (for example, Japanese Patent Laid-Open Publication No. 2002-313967).
The semiconductor memory device shown in this reference includes a memory cell device 1 composed of MONOS transistors, and a peripheral circuit portion 2 constituting a logic circuit composed of MOS transistors, as shown in a plan view of FIG. 41. The peripheral circuit portion 2 further includes low voltage transistors having a thin gate oxide layer, and high voltage transistors having a thick gate oxide layer.
FIG. 42 shows a first example of an equivalent circuit diagram of the memory cell device 1 shown in FIG. 41. This drawing especially shows an AND structure.
As shown in FIG. 42, the memory cell device 1 is composed of transistors M01, M02, M03, . . . , M11, M22, M33, . . . , M153 which are arranged in a matrix form. Each transistor has a known MONOS structure, includes a charge accumulating layer in its floating gate, and has an EEPROM function.
A plurality of word lines WL0, WL1, WL2, WL3-WL14, and WL15 for selecting data items are connected to the memory cell device 1 having the aforementioned structure. The word line WL0 is connected to the control gates of the transistors M01, M02, and M03, and the word line WL1 is connected to the control gates of the transistors M11, M12, and M13. The rest of the word lines (up to WL15) are connected to the control gates of the corresponding transistors in the same manner.
The transistors M01, M11, and M21-M151 are connected in parallel with each other. One end (drain side) of each of these transistors is connected to a bit line BL1, which serves as a data transmitting line, via a selection transistor SS1, and the other end (source side) is connected to a common source line SL via a selection transistor GS1. Similarly, the transistors M02, M12, M22-M152 are connected in parallel with each other, one end is connected to a bit line BL2 via a selection transistor SS2, and the other end is connected to the common source line SL via a selection transistor GS2. The same applies to the transistors M03, M13, and M23-M153.
The memory cell device 1, which is of so-called AND type, is formed with such a structure. Since the operation of such a memory cell device is well known, the explanation thereof is omitted.
FIG. 43 shows a second example of an equivalent circuit diagram of the memory cell device 1 shown in FIG. 1. This drawing especially shows a NOR type structure.
As shown in FIG. 43, the memory cell device 1 is composed of transistors M01, M02, . . . , M11, M12, . . . , and M22 arranged in a matrix form. Each transistor has a known MONOS structure, includes a charge accumulating layer in its floating gate, and has an EEPROM function.
A plurality of word lines WL0, WL1, WL2, . . . serving as data selecting lines, are connected to the memory cell device 1 having the aforementioned basic structure. The word line WL0 is connected to the control gates of the transistor M01 and M02, and the word line WL1 is connected to the control gates of the transistors M11 and M12. The rest of the word lines are connected to the control gates of the corresponding transistors in the same manner.
One end (drain side) of each of the transistors M01, M11, and M21 is connected to a bit line BL1, which serves as a data transmitting line, and the other end (source side) is connected to a common source line SL.
The memory cell device 1, which is of so-called NOR type, is formed with such a structure. Since the operation of such a memory cell device is well known, the explanation thereof is omitted.
FIG. 44 shows a third example of an equivalent circuit diagram of the memory cell device shown in FIG. 41. In particular, this drawing shows the structure of a virtual ground array type memory cell device.
As shown in FIG. 44, the memory cell device 1 is composed of transistors M(m), M(m)′, M(m+1), M(m+1)′, . . . . Each transistor has a known MONOS structure, includes a charge accumulating layer in its floating gate, and has an EEPROM function.
A plurality of word lines WL(m), WL(m+1), . . . serving as data selecting lines, are connected to the memory cell device 1 having the aforementioned basic structure. The word line WL(m) is connected to the control gates of the transistors M(m), M(m)′ . . . , and the word line WL(m+1) is connected to the control gates of the transistors M(m+1), M(m+1)′, . . . .
The transistors M(m) and M(m+1), or M(m)′ and M(m+1)′ are arranged in parallel with each other. One end (drain side) of each transistor is connected to a bit line BL(n), which serves as a data transmitting line, via a selection transistor SS2, and the other end (source side) is connected to a bit line BL(n+1) via a selection transistor SS1 or SS3.
The memory cell device 1, which is of so-called virtual ground array type, is formed with such a structure. Since the operation of such a memory cell device is well known, the explanation thereof is omitted.
FIG. 45 shows a fourth example of an equivalent circuit diagram of the memory cell device shown in FIG. 41. In particular, this drawing shows the structure of the memory cell device 1 employing known NAND type EEPROM.
As shown in FIG. 45, MOS transistors M0, M1, M2, M3, . . . , M14, and M15 constituting one bundle of the memory cell device 1 are connected in series. Each transistor has a known MONOS structure, and has a non-volatile memory function obtained by MIS transistors having charge accumulating electrodes. The gate electrode, i.e., control gate, of each transistor is connected to word lines, i.e., data selecting lines, WL0-WL15. Further, a well potential Well is applied to the back gates of the transistors M0-M15.
The transistor M0, which is located at one end of the series-connected transistors M0-M15, is connected to a bit line BL via a selection transistor S1. The transistor M15, which is located at the other end, is connected to a source line SL via a selection transistor S2. The gate of the selection transistor S1 is connected to a SSL signal line, and the gate of the selection transistor S2 is connected to a GSL signal line.
The SSL signal line and the GSL signal line, which are block selecting lines, are connected to the memory cell device 1. At least one block selecting line is necessary for one block. Such a block selecting line is arranged in the same direction of the data selecting lines WL0-WL15 for the purpose of, e.g., higher integration.
A so-called NAND cell block is formed with such a structure. Since the operation of such a NAND cell block is well known, the explanation thereof is omitted.
FIG. 46 shows a partial plan view pattern of a semiconductor memory device including a memory cell device 1 having the structure shown in FIG. 45. In order to help easy understanding of the cell structure, the drawing shows only the portions under the control gate electrodes.
As can be understood from FIG. 46, the memory cell device 1 includes a plurality of bit lines BL extending in the vertical direction in the drawing. A plurality of word lines WL0-WL15 extending in the horizontal direction in the drawing are formed under the bit lines BL viewing in the thickness direction. An element isolation region 7 is formed between adjacent two word lines, except for the portions under the bit lines BL so as to isolate source and drain regions 8. Bit line contacts 4 are formed on the source and drain regions 8 of the bit lines BL which are adjacent to the SSL signal line. Source line contacts 3 are formed in regions of the bit line BL which are adjacent to the GSL signal line.
FIG. 47 shows sectional views of a conventional semiconductor memory device, in which (A) shows a sectional view taken along line A-A′ of FIG. 46, (B) shows a sectional view taken along line B-B′ of FIGS. 46, and (C) and 47(D) show sectional views of the peripheral circuit portion 2 of FIG. 41. The section (A) corresponds to the gate portion of the memory cell device 1, the section (B) corresponds to the element isolating portion of the memory cell device 1, the section (C) corresponds to a low voltage transistor portion of the peripheral circuit portion 2, and the section (D) corresponds to a high voltage transistor portion of the peripheral circuit portion 2.
As shown in the sections (A) and (B) of FIG. 47, in the region of memory cell device 1, an n-type well 10 is formed on a p-type substrate 9, and a p-type well 11 containing an impurity, e.g., boron or indium, at a concentration of 1014-1019 (cm−3) is formed on the n-type well 10. That is, a substrate 26 of the region of the memory cell device 1 is constituted by forming the n-type well 10 and the p-type well 11 on the p-type substrate 9.
In the region of the memory cell device 1, a tunnel insulating layer 12 serving as a first insulating layer and formed of a silicon oxide layer or an oxynitride layer having a thickness of, e.g., 0.5-10 nm, is formed in a region sandwiched by the source and drain regions 8 of the substrate 26.
Furthermore, a charge accumulating layer 13 of, e.g., a silicon nitride layer, having a thickness of 3-50 nm is formed on the tunnel insulating layer 12.
A block insulating layer 14 of, e.g., a silicon oxide layer or an oxynitride layer, is formed on the charge accumulating layer 13.
Thus, an ONO layer 15 composed of a laminated structure including the tunnel insulating layer 12, the charge accumulating layer 13, and the block insulating layer 14 is formed.
Subsequently, a first gate electrode 18 of a polycrystalline silicon layer is formed on the ONO layer 15, the impurity concentration, e.g., the phosphorus concentration, of the first gate electrode 18 being 1×1019−1×1021 (cm−3).
A metal lining layer of, e.g., WSi, NiSi, MoSi, TiSi, CoSi, etc. having a thickness of 1-500 nm is formed on the first gate electrode 18. The metal lining layer serves as a second gate electrode 19.
Then, a mask insulating layer 20 of a silicon oxide layer or a silicon nitride layer having a thickness of 10-300 nm is formed on the second gate electrode 19.
In the gate region thus formed, a sidewall insulating layer 37 is formed at the sidewall of each transistor.
Furthermore, a barrier insulating layer 21 and an interlayer insulating layer 22 are formed thereon, and a bit line BL is arranged on the interlayer insulating layer 22. A bit contact 4 connects the bit line BL and the source and drain region 8.
In the region of memory cell device 1, the p-type well 11 is isolated from the p-type substrate 9 by means of the n-type well 10. Accordingly, it is possible to apply a voltage to the p-type well 11 independently of the p-type substrate 9. Such a structure is preferable in order to decrease the load of the booster circuit at the time of erasing memory cells, thereby reducing the power consumption.
As shown in the section (C) of FIG. 47, in the low voltage transistor region (LV region) of the peripheral circuit portion 2, the substrate 26 is composed of the p-type substrate 9 and the p-type well 11 formed thereon.
In the low-voltage transistor region, a gate insulating layer 16 of a silicon oxide layer or an oxynitride layer having a thickness of, e.g., 0.5-10 nm is formed in a region sandwiched by the source and drain regions 8 of the substrate 26. A first gate electrode 18 of polycrystalline silicon layer having a thickness of 10-500 nm is formed on the gate insulating layer 16.
A metal lining layer of, e.g., WSi, NiSi, MoSi, TiSi, CoSi, etc., having a thickness of 1-500 nm is formed on the first gate electrode 18, thereby forming a second gate electrode 19.
Subsequently, a mask insulating layer 20 of a silicon oxide layer or a silicon nitride layer having a thickness of 10-300 nm is formed on the second gate electrode 19.
A sidewall insulating layer 37 is formed at the sidewall of each transistor thus formed.
Furthermore, a barrier insulating layer 21 and an interlayer insulating layer 22 are formed thereon, and a signal line 24 is arranged on the interlayer insulating layer 22. A contact 25 connects the signal line 24 and the source and drain region 8.
As shown in the section (D) of FIG. 47, in the high voltage transistor region (HV region), a gate insulating layer 17 of a silicon oxide layer or an oxynitride layer having a thickness of, e.g., 10-50 nm is formed in a region sandwiched by the source and drain regions 8 on the p-type substrate 9. A first gate electrode 18 of polycrystalline silicon layer having a thickness of 10-500 nm is formed on the gate insulating layer 17.
A metal lining layer of, e.g., WSi, NiSi, MoSi, TiSi, CoSi, etc., having a thickness of 1-500 nm is formed on the first gate electrode 18, thereby forming a second gate electrode 19.
Subsequently, a mask insulating layer 20 of a silicon oxide layer or a silicon nitride layer having a thickness of 10-300 nm is formed on the second gate electrode 19.
A sidewall insulating layer 37 is formed at the sidewall of each transistor thus formed.
Furthermore, a barrier insulating layer 21 and an interlayer insulating layer 22 are formed thereon, and a signal line 24 is arranged on the interlayer insulating layer 22. A contact 25 connects the signal line 24 and the source and drain region 8.
The gate insulating layer 17 in the high voltage transistor region is thicker than the gate insulating layer 16 of the low voltage transistor region in order to improve the withstand voltage.
As shown in the sections (B), (C), and (D) of FIG. 47, STI grooves (trench grooves) serving as element isolation grooves 6 and 23 are formed in order to isolate elements in the element isolation region of the memory cell device 1, and the low voltage transistor regions and the high voltage transistor region of the peripheral circuit portion 2.
Furthermore, a p-type region 27 including an impurity is formed at the bottom of each element isolation groove 23 in the high voltage transistor region, as shown in the section (D) of FIG. 47. It is preferable that the impurity concentration of the p-type region 27 is higher than that of the p-type substrate 9 in order to improve the element isolation withstand voltage.
As is apparent from the sections (B) and (C) of FIG. 47, a relatively deep element isolation grooves (relatively deep trench grooves) 6 are formed in the region of memory cell device 1 and the low voltage transistor region of the peripheral circuit portion 2.
As is apparent from the section (D) of FIG. 47, a relatively shallow element isolation groove (relatively shallow trench groove) 23 is formed in the high voltage transistor region of the peripheral circuit portion 2.
Next, a method of manufacturing the conventional semiconductor memory device having the aforementioned structure will be described with reference to FIGS. 48-50.
In FIGS. 48-50, the sections (A), (B), (C), and (D) correspond to those of FIG. 47.
In order to simplify the explanation, the n-type well 10 and p-type well 11 located on the p-type substrate 9, and the p-type region 27 at the bottom of the element isolation groove 23 are not shown in FIGS. 48-50. These are inclusively referred to as the substrate 26.
First, a sacrificial oxide layer (not shown) having a thickness of 5-15 nm is formed on the substrate 26. Then, if a need arises, an impurity is doped into the well and channel portions of the memory cell device 1 and the peripheral circuit portion 2, thereby forming the basic structure of the substrate 26.
Thereafter, the sacrificial oxide layer is removed, and a silicon oxide layer or a silicon nitride layer to become the gate insulating layer 17 in the high voltage transistor region of the peripheral circuit portion 2 is formed on the entire surface of the substrate 26. The thickness of the gate insulating layer 17 is adjusted to be, e.g., about 400 nm so that even if the thickness changed in the subsequent steps, the target thickness could be ultimately achieved.
Subsequently, the high voltage transistor region is covered by a resist, and the gate insulating layer 17 is removed from the memory cell region and the low voltage transistor region. As a result, the gate insulating layer 17 remains only in the high voltage transistor region.
Then, the resist is removed, and a silicon oxide layer or a silicon nitride layer having a thickness of 0.5-5 nm is formed as the tunnel insulating layer 12 of the MONOS memory cell. Thereafter, an insulating layer formed of, e.g., silicon oxide, silicon nitride, HfO2, TA2O5, TiO2, Al2O3, etc., is deposited, thereby forming the charge accumulating layer 13.
The block insulating layer 14 of a silicon oxide layer or a silicon nitride layer having a thickness of 1-20 nm is formed on the charge accumulating layer 13.
After the aforementioned steps, the ONO layer 15 having a three-layer structure including the tunnel insulating layer 12, the charge accumulating layer 13, and the block insulating layer 14 is formed in the memory cell region and the low voltage transistor region, and the ONO layer 15 including the gate insulating layer 17, the charge accumulating layer 13, and the block insulating layer 14 is formed in the high voltage transistor region.
Subsequently, a silicon nitride layer having a thickness of 10-500 nm, serving as a stopper layer 30 for stopping the CMP step for flattening a material embedding in the element isolation region, is deposited. Furthermore, a silicon oxide layer having a thickness of 10-500 nm is deposited on the stopper layer 30, the silicon oxide layer serving as a mask member 31 to be used for anisotropic etching of the element isolation region.
The sectional views of the respective regions as shown in FIGS. (A)-(D) of FIG. 48 can be obtained through the aforementioned steps. As is apparent from FIG. 48, the gate insulating layer 17 of the high voltage transistor region is thicker than the tunnel insulating layer 12 of the gate region, the element isolation region, and the low voltage transistor region. As a result, the upper surface of the mask material 31 in the high voltage transistor region is higher than that in the other regions.
Then, as shown in FIG. 49, a resist (not shown) is patterned by photolithography, and then anisotropic etching is performed on the mask member 31 and the stopper layer 30.
Thereafter, as shown in FIG. 50, the block insulating layer 14, the charge accumulating layer 13, the tunnel insulating layer 12, the gate insulating layer 17, and the p-type well 11 is etched up to a predetermined depth by anisotropic etching, thereby forming trenches serving as the element isolation grooves 6 of the element isolation region and the low voltage transistor region, and the element isolation groove 23 of the high voltage transistor region.
As shown in the sections (B), (C), and (D) of FIG. 50, since the gate insulating layer 17 of the high voltage transistor region is thicker than the tunnel insulating layer 12 of the element isolation region and the low voltage transistor region, the element isolation groove 23 of the high voltage transistor region is adjusted to be deeper than the element isolation grooves 6 of the element isolation regions and the low voltage transistor region so as to compensate for the difference in thickness.
The size of the transistors in the region of the memory cell device 1 shown in the sections (A)s and (B)s of FIGS. 48-50 is relatively smaller than the size of the transistors in the region of the peripheral circuit portion 2 in the sections (C)s and (D)s of FIGS. 48-50. As a result, the width of the element isolation groove 6 and the distance between adjacent two element isolation grooves 6 in the region of the memory cell device 1 are adjusted to be smaller.
In addition to the aforementioned steps, the steps as disclosed in Japanese Patent Laid-Open Publication No. 2002-313967, which was mentioned before as the prior art reference, are performed to achieve the semiconductor memory device as shown in the sectional view of FIG. 47.
Generally, it is preferable that the element isolation grooves 6 and 23 were relatively deeper in order to obtain a higher element isolation withstand voltage. That is, it is preferable that the element isolation groove 23 were as deep as possible in order to improve the withstand voltage of the high voltage transistor region. Here, the depth of an element isolation groove is defined to be the distance between the upper surface of the substrate 26 and the bottom of the element isolation groove.
In the memory region, however, since the improvement in integration and miniaturization of device is the important objective in order to achieve a mass storage device, the width of the element isolation groove 6 and the distance between the adjacent two element isolation grooves 6 should be adjusted to be reduced. At this time, in order to facilitate the manufacture and improve the yield, the element isolation grooves 6 and 23 in this region should be as shallow as possible. The reason for this is that when the trench groove is deep, the embedding aspect ratio at the time of filling up the trench groove becomes higher. As a result, it becomes difficult to achieve a good embedding characteristic.
However, in the conventional semiconductor memory device and a method of manufacturing the conventional semiconductor memory device, the element isolation groove 23 of the high voltage transistor region is shallower than the element isolation groove 6 of the memory cell region or the low voltage transistor region.
Since the conventional semiconductor memory device has the aforementioned structure, and the process of the method of manufacturing the conventional semiconductor memory device is carried out in the manner mentioned above, the following problems have been raised.
In a high voltage transistor region, the element isolation groove 23, which should be formed as deep as possible in order to obtain a higher element isolation withstand voltage, is shallower than that in other regions. Thus, it is difficult to improve the withstand voltage.
In the memory region, the element isolation groove 6, which should be formed as shallow as possible in order to improve the manufacturing yield, is formed relatively deep. Thus, it is difficult to improve the manufacturing yield.
Furthermore, in the low voltage transistor region of the peripheral circuit portion 2, it is not necessary to form the element isolation groove 6 to be deep at a sacrifice of the manufacture yield since the voltage applied to the low voltage transistor region is not so high.
Thus, the aforementioned conventional semiconductor memory device and the method of manufacturing such a semiconductor memory device have problems in that the trench grooves in the region of memory cell device 1, which should be as shallow as possible in order to improve the yield, are formed deep, and that the trench grooves in the high voltage transistor region of the peripheral circuit portion 2, which should be as deep as possible in order to improve the element isolation withstand voltage, are formed shallow.